射频电路和射频集成电路设计中的关键课题

ISBN: 9787040159585

出版社: 高等教育出版社

出版年: 2005-2

页数: 395

定价: 40.10元

装帧: 简裝本

内容简介

《射频电路和射频集成电路设计中的关键课题》总共十二章，涵盖六个关键性的课题：1）阻抗匹配；2）射频接地；3）单端和差分线路；4）误差分析；5）展望射频集成电路设计；6）射频电路的基本参数和指标。

射频电路设计中最大的特点是阻抗匹配。没有阻抗匹配的电路设计就不是射频电路设计。阻抗匹配也是射频电路设计和数码电路设计的主要差別之处。由于它的重要性, 《射频电路和射频集成电路设计中的关键课题》的第一章和第二章比较详细地讨论了这一关键性课题。其余的章节是在射频电路设计中最需要的基本知识，包括：什么是射频电路的基本参数？为什么目前在射频和射频集成电路设计中出现从单端转化为差分结构的趋势？射频集成电路设计的主要难题是什么？如何克服这些障碍? 在射频电路设计中，射频电路单元性能的好坏往往取决于射频接地的成功与否。射频电路的误差分析则关系到产品合格率，而产品合格率是一间公司的生命线。

《射频电路和射频集成电路设计中的关键课题》有两个特色。

首先，在已出版了的大多数射频电路和射频集成电路设计的书中,其內容是讨论一个个射频电路单元,譬如,低噪声放大器,混频器,功率放大器, 压控振蕩器,頻率综合器。因此，可以把它们归类为纵向论述的书。《射频电路和射频集成电路设计中的关键课题》则不是讨论一个个射频电路单元, 而是着重论述和強调在射频电路和射集成电路设计中共同的关键性课题，因此，这是一本橫向论述的书。其次，尽管有些内容是引自出版了的书刊和文献。在本讲座中不少内容是引自《射频电路和射频集成电路设计中的关键课题》作者的设计和工作报告。

《射频电路和射频集成电路设计中的关键课题》可作为以下读者在射频电路和射频集成电路的设计，研究和学习中的参考书：

射频电路和射频集成电路设计工程师,测试工程师,系统工程师和经理；

射频电路和射频集成电路的有关研究人员；

射频电路和射频集成电路有关专业的大学本科生，研究生和教授。

作者简介

Richard Chi-Hsi Li，male， was born in NanAn，QuanZhou ，Fujian，China .He graduated in the Physics Department of FuDan Unversity，Shanghai，China in 1985.From 1958 to 1973 .he and been working for the Institute of Geophysics ，Chineseacademy and the University of China Science and Technology，Beijing， China.

Chapter 1 Importance of Impedance Matching
1．1 Difference between RF and Digital Circuit Design
1．1．1 Case 1: Digital Circuits at Low Data Rate
1．1．2 Case 2: Digital Circuits at High Data Rate
1．2 Significance of Impedance Matching
1．2．1 Power Transportation from a Source to a Load
1．2．2 Maximizing of Power Transportation without Phase Shift
1．2．3 Conjugate Impedance Matching and Voltage Reflection Coefficient
1．2．4 Impedance Matching Networ
1．3 Problems due to Unmatched Status of Impedance
1．3．1 General Expression of Power Transportation
1．3．2 Power Instability and Additional Power Los
1．3．3 Additional Distortion and Quasi-Noise
1．3．4 Power Measurement
1．3．5 Power Transportation and Voltage Transportatio
1．3．6 Burning of a Transistor
References
Chapter 2 Impedance Matching
2．1 Impedance Measured by Small Signal
2．1．1 Impedance Measured by S Parameter Measurement
2．1．2 The Smith Chart: Impedance and Admittance Coordinatio
2．1．3 Accuracy of Smith Chartl
2．1．4 Relationship between the Impedance in Series and in Parallel
2．2 Impedance Measured by Large Signal
2．3 Impedance Matching
2．3．1 One Part Matching Network
2．3．2 Recognition of Regions in a Smith Chart
2．3．3 Two Parts Matching Network
2．3．4 Two Parts Upward and Downward Impedance Transformer
2．3．5 Three Parts Matching Network and Impedance Transformer
2．3．5．1 Topology Limitation of Two Parts Matching Network
2．3．5．2 Π Type Matching Network
2．3．5．3 T Type Matching Network
2．4 Some Useful Schemes for Impedance Matching
2．4．1 Designs and Tests when ZL is not 50 Ω
2．4．2 Conversion between“T” and “Π” Type Matching Network
2．4．3 Parts in a Matching Network
2．4．4 Impedance Matching between Power Transportation Units
2．4．5 Impedance Matching for a Mixer
References
Chapter 3 RF Grounding
3．1 A True Story
3．2 Three Components for RF Grounding
3．2．1 “Zero” Capacitors
3．2．2 Micro Strip Line
3．2．3 RF Cable
3．3 Examples of RF grounding
3．3．1 Test PCB
3．3．1．1 Small Test PCB
3．3．1．1．1 Basic Types of Test PCB
3．3．1．1．2 RF Grounding with a Rectngular Metallic Frame
3．3．1．1．3 An Example
3．3．1．2 Large Test PCB
3．3．1．2．1 RF Grounding by “Zero” Chip Capacitors
3．3．1．2．2 RF Grounding by a Runner or a Cable with Half or Quarter Wavelength
3．3．2 Isolation between Input and Output in a Mixer or an Up-converter
3．3．3 Calibration for Network Analyzer
3．4 RF Grounding for Reduction of Return Current Coupling
3．4．1 A Circuit Built by Discrete Parts on a PCB
3．4．2 RFICs
References
Chapter 4 Equivalent Circuits of Passive Chip Parts
4．1 Modeling of Passive Chip Parts
4．2 Characterizing of Passive Chip Parts by Network Analyzer
4．3 Extraction from the Measurement by Network Analyzer
4．3．1 Chip Capacitor
4．3．2 Chip Inductor
4．3．3 Chip Resistor
4．4 Summary
References
Chapter 5 Single-ended Stage and Differential Pair
5．1 Basic Single-ended Stage
5．1．1 General Description
5．1．2 Small Signal Model of a Bipolar Transistor
5．1．2．1 Impedance of a CE (Common Emitter) Device
5．1．2．2 Impedance of a CB (Common Base) Device
5．1．2．3 Impedance of a CC (Common Collector) Device
5．1．2．4 Comparison between CE， CB， and CC Device
5．1．3 Small-signal Model ofa MOSFET
5．1．3．1 Impedance of a CS (Common Source) Device
5．1．3．2 Impedance ofa CG (Common Gate) Device
5．1．3．3 Impedance of a CD (Common Drain) Device
5．1．3．4 Comparison between CS， CG， and CD Device
5．2 Differential Pair
5．2．1 DC Transfer Characteristic
5．2．1．1　DC Transfer Characteristic of a Bipolar Differential Pair
5．2．1．2 DC Transfer Characteristic of a CMOS Differential Pair
5．2．2 Small Signal Characteristic
5．2．3 Improvement of CMRR
5．2．4 Increase of Voltage Swing
5．2．5 Cancellation of Interference
5．2．6 Noise in a Differential Pair
5．3 Apparent Difference between Single-ended Stage and Differential Pair
5．4 DC Offset
5．4．1 DC Offset in a Single-ended Device
5．4．2 Zero DC Offset in a Pseudo-Differential Pair
5．4．3 Why "Zero" IF or Direct Conversion
5．4．4 DC Offset Cancellation
5．4．4．1　"Chopping" Mixer
5．4．4．2 DC Offset Calibration
5．4．4．3 Hardware Schemes
References
Chapter 6 Balun
6．1 Coaxial Cable Balun
6．2 Ring Micro Strip Line Balun
6．3 Transformer Balun
6．4 Transformer Balun Composed by Two Stacked 22 Transformers
6．5 LCBalun
References
Chapter 7 Tolerance Analysis
7．1 Importance of Tolerance Analysis
7．2 Fundamentals of Tolerance Analysis
7．2．1 Tolerance and Normal Distribution
7．2．2 6a， Cp， and Cp，
7．2．3 Yield Rate and DPU
7．2．4 Poisson Distribution
7．3 An Approach to 6a Design and Production
7．4 An Example: A Tunable Filter Design
7．4．1 Description of the Tunable Filter Design
7．4．2 Monte-Carlo Analysis
7．5 Appendix: Table of the Normal Distribution
References
Chapter 8 Prospect of RFIC Design269
Chapter 9 Noise， Gain， and Sensitivity of a Receiver317
Chapter 10 Non-linearity and Spurious Products339
Chapter 11 Cascaded Equations and System Analysis 358
Chapter 12 From Analog to Digital Communication System376

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